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june 2004 ? cypress microsystems, inc. 2004 ? document no. 38-12019 rev. *b 1 psoc? mixed signal array preliminary data sheet cy8c27466, cy8c27566, and cy8c27666 psoc? functional overview the psoc? family consists of many mixed signal array with on-chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one, low cost single-chip programmable device. psoc devices include configurable blocks of analog and digital logic, as well as programmable interconnects. this architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable io are included in a range of conve- nient pinouts and packages. the psoc architecture, as illustrated on the left, is comprised of four main areas: psoc core, digital system, analog system, and system resources. configurable global busing allows all the device resources to be combined into a complete custom system. the psoc cy8c27x66 family can have up to five io ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks. the psoc core the psoc core is a powerful engine that supports a rich fea- ture set. the core includes a cpu, memory, clocks, and config- urable gpio (gene ral purpose io). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture micro- processor. the cpu utilizes an interrupt controller with 18 vec- features powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? two 8x8 multiply, 32-bit accumulate ? low power at high speed ? 3.0 to 5.25 v operating voltage ? operating voltages down to 1.0v using on- chip switch mode pump (smp) ? industrial temperature range: -40c to +85c advanced peripherals (psoc blocks) ? 12 rail-to-rail analog psoc blocks provide: - up to 14-bit adcs - up to 9-bit dacs - programmable gain amplifiers - programmable filters and comparators ? 8 digital psoc blocks provide: - 8- to 32-bit timers, counters, and pwms - crc and prs modules - up to 2 full-duplex uarts - multiple spi ? masters or slaves - connectable to all gpio pins ? complex peripherals by combining blocks precision, programmable clocking ? internal 2.5% 24/48 mhz oscillator ? 24/48 mhz with optional 32.768 khz crystal ? optional external oscillator, up to 24 mhz ? internal oscillator for watchdog and sleep flexible on-chip memory ? 32k bytes flash program storage 50,000 erase/write cycles ? 1k bytes sram data storage ? in-system serial programming (issp ? ) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 12 analog inputs on gpio ? four 40 ma analog outputs on gpio ? configurable interrupt on all gpio additional system resources ? i 2 c ? slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc? designer) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k bytes trace memory ? complex events ? c compilers, assembler, and linker digital system sram 1k interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 32k digital block array two multiply accum. switch mode pump internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog block array analog ref analog input muxing i c 2 (2 rows, 8 blocks) (4 columns, 12 blocks) port 5 port 4 port 3 port 2 port 1 port 0 analog drivers system bus
june 1, 2004 document no. 38-12019 rev. *b 2 cy8c27x66 preliminary data sheet psoc? overview tors, to simplify programming of real time embedded events. program execution is timed and protected using the included sleep and watch dog timers (wdt). memory encompasses 32k of flash for program storage, 1 kb of sram for data storage, and up to 2k of eeprom emulated using the flash. program flash utilizes four protection levels on blocks of 64 bytes, allowing customized software ip protection. the psoc device incorporates flexible internal clock genera- tors, including a 24 mhz imo (internal main oscillator) accurate to 2.5% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. if crystal accuracy is desired, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc) and can optionally generate a crys- tal-accurate 24 mhz system clock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfac- ing. every pin also has the capability to generate a system inter- rupt on high level, low level, and change from last read. the digital system the digital system is composed of 8 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. digital peripheral configura- tions include those listed below. pwms (8 to 32 bit) pwms with dead band (8 to 32 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity (up to 2) spi master and slave (up to 2 each) i2c slave and master (1 available as a system resource) cyclical redundancy checker/generator (8 to 32 bit) irda (up to 2) pseudo random sequence generators (8 to 32 bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the con- straints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device family. this allows you the opti- mum choice of system resources for your application. family resources are shown in the table titled ?psoc device charac- teristics? on page 3 . digital system block diagram the analog system the analog system is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexi- ble and can be customized to support specific application requirements. some of the more common psoc analog func- tions (most available as user modules) are listed below. analog to digital converters (up to 4, with 6- to 14-bit resolu- tion, selectable as incremental, delta sigma, and sar) filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch) amplifiers (up to 4, with selectable gain to 48x) instrumentation amplifiers (up to 2, with selectable gain to 93x) comparators (up to 4, with 16 selectable thresholds) dacs (up to 4, with 6- to 9-bit resolution) multiplying dacs (up to 4, with 6- to 9-bit resolution) high current output drivers (four with 40 ma drive as a core resource) 1.3v reference (as a system resource) dtmf dialer modulators correlators digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 1 dbb10 dbb11 dcb12 dcb13 row input configuration 4 4 row output configuration row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 5 port 4 port 3 port 2 port 1 port 0
june 1, 2004 document no. 38-12019 rev. *b 3 cy8c27x66 preliminary data sheet psoc? overview peak detectors many other topologies possible analog blocks are provided in columns of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks. the number of blocks is dependant on the device family which is detailed in the table titled ?psoc device characteris- tics? on page 3 . analog system block diagram additional system resources system resources, some of which have been previously listed, provide additsnrional capability useful to complete systems. additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. brief statements describing the merits of each system resource are presented below. digital clock dividers provide three customizable clock fre- quencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate to assist in both general math as well as digital filters. the decimator provides a custom hardware filter for digital signal, processing applications including the creation of delta sigma adcs. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute refer- ence for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2v battery cell, providing a low cost boost converter. psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. the following table lists the resources available for specific psoc device groups. acb00 acb01 block array array input configuration aci1[1:0] aci2[1:0] acb02 acb03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandga p refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference psoc device characteristics psoc part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks cy8c29x66 up to 64 4 16 12 4 4 12 cy8c27x66 up to 44 2 8 12 4 4 12 cy8c27x43 up to 44 2 8 12 4 4 12 cy8c24x23 up to 24 1 4 12 2 2 6 cy8c22x13 up to 16 1 4 8 1 1 3
june 1, 2004 document no. 38-12019 rev. *b 4 cy8c27x66 preliminary data sheet psoc? overview getting started the quickest path to understanding the psoc silicon is by read- ing this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an over- view of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in-depth information, along with detailed programming information, reference the psoc? mixed signal array technical reference manual . for up-to-date ordering, packaging, and electrical specification information, reference the latest psoc device data sheets on the web at http://www.cypress.com/psoc. development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store at http://www.onfulfillment.com/cypressstore/ contains develop- ment kits, c compilers, and all accessories for psoc develop- ment. click on psoc (programmable system-on-chip) to view a current list of available items. tele-training free psoc "tele-training" is available for beginners and taught by a live marketing or application engineer over the phone. five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes cover- ing topics like psoc and the lin bus. for days and times of the tele-training, see http://www.cypress.com/support/training.cfm . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant, go to the following cypress support web site: http://www.cypress.com/support/cypros.cfm . technical support psoc application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm . application notes a long list of application notes will assist you in every aspect of your design effort. to locate the psoc application notes, go to http://www.cypress.com/design/results.cfm . development tools the cypress microsystems psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide and application runs on windows 98, windows nt 4.0, windows 2000, windows millennium (me), or windows xp. (reference the psoc designer functional flow diagram below.) psoc designer helps the customer to select an operating con- figuration for the psoc, write application code that uses the psoc, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high-level c language compiler developed specifically for the devices in the family. psoc designer subsystems commands results psoc tm designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer interface context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc tm designer
june 1, 2004 document no. 38-12019 rev. *b 5 cy8c27x66 preliminary data sheet psoc? overview psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic configu- ration allows for changing configurations at run time. psoc designer sets up power-on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of psoc block configurations at run time. psoc designer can print out a configuration sheet for given project configuration for use during application program- ming in conjunction with the device data sheet. once the framework is generated, the user can add application-specific code to flesh out the framework. it?s also possible to change the selected components and regenerate the framework. design browser the design browser allows users to select and import precon- figured designs into the user?s project. users can easily browse a catalog of preconfigured designs to facilitate time-to-design. examples provided in the tools include a 300-baud modem, lin bus master and slave, fan controller, and magnetic card reader. application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, com- pile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c code. the link libraries auto- matically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports cypress microsystems? psoc family devices. even if you have never worked in the c language before, the product quickly allows you to create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write io registers, read and write cpu registers, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is avail- able for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of the parallel or usb port. the base unit is universal and will operate with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. psoc development tool kit
june 1, 2004 document no. 38-12019 rev. *b 6 cy8c27x66 preliminary data sheet psoc? overview user modules and the psoc development process the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses, and to the io pins. iterative development cycles permit you to adapt the hard- ware as well as the software. this substantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer inte- grated development environment (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library con- tains over 50 common peripherals such as adcs, dacs tim- ers, counters, uarts, and other not-so common peripherals such as dtmf generators and bi-quad analog filter sections. each user module establishes the basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user mod- ule configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high- level functions to control and respond to hardware events at run-time. the api also provides optional interrupt service rou- tines that you can adapt as needed. the api functions are documented in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specifications. each data sheet describes the use of each user module parameter and documents the set- ting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a pictorial environment (gui) for configuring the hardware. you pick the user modules you need for your project and map them onto the psoc blocks with point- and-click simplicity. next, you build signal chains by intercon- necting user modules to each other and the io pins. at this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the high-level user module api functions. user module and source code development flows the next step is to write your main program, and any sub-rou- tines using psoc designer?s application editor subsystem. the application editor includes a project manager that allows you to open the project source code files (including all gener- ated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a profes- sional-strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as nec- essary. project-level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a rom file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger down- loads the rom image to the in-circuit emulator (ice) where it runs at full speed. debugger capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator
june 1, 2004 document no. 38-12019 rev. *b 7 cy8c27x66 preliminary data sheet psoc? overview document conventions acronyms used the following table lists the acronyms that are used in this doc- ument. units of measure a units of measure table is located in the electrical specifica- tions section. table 3-1 on page 15 lists all the abbreviations used to measure the psoc devices. numeric naming hexidecimal numbers are represented with all letters in upper- case with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (e.g., 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or 0x are decimal. table of contents for an in depth discussion and more information on your psoc device, obtain the psoc mixed signal array technical refer- ence manual . this document encompasses and is organized into the following chapters and sections. 1. pin information ............................................................. 8 1.1 pinouts ................................................................... 8 1.1.1 28-pin part pinout ..................................... 8 1.1.2 44-pin part pinout ..................................... 9 1.1.3 48-pin part pinouts .................................. 10 2. register reference ..................................................... 12 2.1 register conventions ........................................... 12 2.1.1 abbreviations used .................................. 12 2.2 register mapping tables ..................................... 12 3. electrical specifications ............................................ 15 3.1 absolute maximum ratings ................................ 16 3.2 operating temperature ....................................... 16 3.3 dc electrical characteristics ................................ 17 3.3.1 dc chip-level specifications ................... 17 3.3.2 dc general purpose io specifications .... 17 3.3.3 dc operational amplifier specifications ... 18 3.3.4 dc analog output buffer specifications ... 19 3.3.5 dc switch mode pump specifications ..... 20 3.3.6 dc analog reference specifications ....... 21 3.3.7 dc analog psoc block specifications ..... 22 3.3.8 dc por, smp, and lvd specifications ... 23 3.3.9 dc programming specifications ............... 24 3.4 ac electrical characteristics ................................ 25 3.4.1 ac chip-level specifications ................... 25 3.4.2 ac general purpose io specifications .... 27 3.4.3 ac operational amplifier specifications ... 28 3.4.4 ac digital block specifications ................. 30 3.4.5 ac analog output buffer specifications ... 31 3.4.6 ac external clock specifications ............. 32 3.4.7 ac programming specifications ............... 32 3.4.8 ac i2c specifications ............................... 33 4. packaging information ............................................... 34 4.1 packaging dimensions ......................................... 34 4.2 thermal impedances .......................................... 37 4.3 capacitance on crystal pins ............................... 37 5. ordering information .................................................. 38 5.1 ordering code definitions ................................... 38 6. sales and service information .................................. 39 6.1 revision history .................................................. 39 6.2 copyrights ............................................................ 39 acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter por power on reset ppor precision power on reset psoc? programmable system-on-chip pwm pulse width modulator ram random access memory rom read only memory sc switched capacitor smp switch mode pump tbd to be determined
may 2004 document no. 38-12019 rev. *b 8 1. pin information this chapter describes, lists, and illustrates the cy8c27x66 psoc device pins and pinout configurations. 1.1 pinouts the cy8c27x66 psoc device is available in a variety of packages which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital io. however, vss, vdd, smp, and xres are not capable of digital io. 1.1.1 28-pin part pinout table 1-1. 28-pin part pinout (pdip, ssop, soic) pin no. type pin name description cy8c27466 28-pin psoc device digital analog 1 io i p0[7] analog column mux input. 2 io io p0[5] analog column mux input and column output. 3 io io p0[3] analog column mux input and column output. 4 io i p0[1] analog column mux input. 5 io p2[7] 6 io p2[5] 7 io i p2[3] direct switched capacitor block input. 8 io i p2[1] direct switched capacitor block input. 9 power smp switch mode pump (smp) connection to external components required. 10 io p1[7] i2c serial clock (scl) 11 io p1[5] i2c serial data (sda) 12 io p1[3] 13 io p1[1] crystal (xtalin), i2c serial clock (scl) 14 power vss ground connection. 15 io p1[0] crystal (xtalout), i2c serial data (sda) 16 io p1[2] 17 io p1[4] optional external clock input (extclk) 18 io p1[6] 19 input xres active high pin reset with internal pull down. 20 io i p2[0] direct switched capacitor block input. 21 io i p2[2] direct switched capacitor block input. 22 io p2[4] external analog ground (agnd) 23 io p2[6] external voltage reference (vref) 24 io i p0[0] analog column mux input. 25 io io p0[2] analog column mux input and column output. 26 io io p0[4] analog column mux input and column output. 27 io i p0[6] analog column mux input. 28 power vdd supply voltage. legend : a = analog, i = input, and o = output. ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] p2[7] p2[5] ai, p2[3] ai, p2[1] smp i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss vdd p0[6], ai p0[4], aio p0[2], aio p0[0], ai p2[6], external vref p2[4], external agnd p2[2], ai p2[0], ai xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sd a pdip ssop soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
june 1, 2004 document no. 38-12019 rev. *b 9 cy8c27x66 preliminary data sheet 1. pin information 1.1.2 44-pin part pinout table 1-2. 44-pin part pinout (tqfp) pin no. type pin name description cy8c27566 44-pin psoc device digital analog 1 io p2[5] 2 io i p2[3] direct switched capacitor block input. 3 io i p2[1] direct switched capacitor block input. 4 io p4[7] 5 io p4[5] 6 io p4[3] 7 io p4[1] 8 power smp switch mode pump (smp) connection to external components required. 9 io p3[7] 10 io p3[5] 11 io p3[3] 12 io p3[1] 13 io p1[7] i2c serial clock (scl) 14 io p1[5] i2c serial data (sda) 15 io p1[3] 16 io p1[1] crystal (xtalin), i2c serial clock (scl) 17 power vss ground connection. 18 io p1[0] crystal (xtalout), i2c serial data (sda) 19 io p1[2] 20 io p1[4] optional external clock input (extclk) 21 io p1[6] 22 io p3[0] 23 io p3[2] 24 io p3[4] 25 io p3[6] 26 input xres active high pin reset with internal pull down. 27 io p4[0] 28 io p4[2] 29 io p4[4] 30 io p4[6] 31 io i p2[0] direct switched capacitor block input. 32 io i p2[2] direct switched capacitor block input. 33 io p2[4] external analog ground (agnd) 34 io p2[6] external voltage reference (vref) 35 io i p0[0] analog column mux input. 36 io io p0[2] analog column mux input and column output. 37 io io p0[4] analog column mux input and column output. 38 io i p0[6] analog column mux input. 39 power vdd supply voltage. 40 io i p0[7] analog column mux input. 41 io io p0[5] analog column mux input and column output. 42 io io p0[3] analog column mux input and column output. 43 io i p0[1] analog column mux input. 44 io p2[7] legend : a = analog, i = input, and o = output. tqfp p3[1] p2[7] p2[5] p2[4], external agn d a i, p2[3] p2[2], ai a i, p2[1] p2[0], ai p4[7] p4[6] p4[5] p4[4] p4[3] p4[2] p4[1] p4[0] smp xres p3[7] p3[6] p3[5] p3[4] p3[3] p3[2] i2c scl, p1[7] p0[1], ai i2c sda, p1[5] p0[3], aio p1[3] p0[5], aio i2c scl, xtalin, p1[1] p0[7], ai vss vdd i2c sda, xtalout, p1[0] p0[6], ai p1[2] p0[4], aio extclk, p1[4] p0[2], aio p1[6] p0[0], ai p3[0] p2[6], external vre f 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 13 14 15 16 17 18 19 20 21 22 12
june 1, 2004 document no. 38-12019 rev. *b 10 cy8c27x66 preliminary data sheet 1. pin information 1.1.3 48-pin part pinouts table 1-3. 48-pin part pinout (ssop) pin no. type pin name description cy8c27666 48-pin psoc device digital analog 1 io i p0[7] analog column mux input. 2 io io p0[5] analog column mux input and column output. 3 io io p0[3] analog column mux input and column output. 4 io i p0[1] analog column mux input. 5 io p2[7] 6 io p2[5] 7 io i p2[3] direct switched capacitor block input. 8 io i p2[1] direct switched capacitor block input. 9 io p4[7] 10 io p4[5] 11 io p4[3] 12 io p4[1] 13 power smp switch mode pump (smp) connection to external components required. 14 io p3[7] 15 io p3[5] 16 io p3[3] 17 io p3[1] 18 io p5[3] 19 io p5[1] 20 io p1[7] i2c serial clock (scl) 21 io p1[5] i2c serial data (sda) 22 io p1[3] 23 io p1[1] crystal (xtalin), i2c serial clock (scl) 24 power vss ground connection. 25 io p1[0] crystal (xtalout), i2c serial data (sda) 26 io p1[2] 27 io p1[4] optional external clock input (extclk) 28 io p1[6] 29 io p5[0] 30 io p5[2] 31 io p3[0] 32 io p3[2] 33 io p3[4] 34 io p3[6] 35 input xres active high pin reset with internal pull down. 36 io p4[0] 37 io p4[2] 38 io p4[4] 39 io p4[6] 40 io i p2[0] direct switched capacitor block input. 41 io i p2[2] direct switched capacitor block input. 42 io p2[4] external analog ground (agnd) 43 io p2[6] external voltage reference (vref) 44 io i p0[0] analog column mux input. 45 io io p0[2] analog column mux input and column output. 46 io io p0[4] analog column mux input and column output. 47 io i p0[6] analog column mux input. 48 power vdd supply voltage. legend : a = analog, i = input, and o = output. ssop ai, p0[7] vdd aio, p0[5] p0[6], ai aio, p0[3] p0[2], aio ai, p0[1] p0[4], aio p2[7] p0[0], ai p2[5] p2[6], external vref ai, p2[3] p2[4], external agnd ai, p2[1] p2[2], ai p4[7] p2[0], ai p4[5] p4[6] p4[3] p4[4] p4[1] p4[2] smp p4[0] p3[7] xres p3[5] p3[6] p3[3] p3[4] p3[1] p3[2] p5[3] p3[0] p5[1] p5[2] i2c scl, p1[7] p5[0] i2c sda, p1[5] p1[6] p1[3] p1[4], extclk i 2c scl, xtalin, p1[1] p1[2] vss p1[0], xtalout, i2c sd a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25
june 1, 2004 document no. 38-12019 rev. *b 11 cy8c27x66 preliminary data sheet 1. pin information table 1-4. 48-pin part pinout (mlf*) pin no. type pin name description cy8c27666 48-pin psoc device digital analog 1 io i p2[3] direct switched capacitor block input. 2 io i p2[1] direct switched capacitor block input. 3 io p4[7] 4 io p4[5] 5 io p4[3] 6 io p4[1] 7 power smp switch mode pump (smp) connection to external components required. 8 io p3[7] 9 io p3[5] 10 io p3[3] 11 io p3[1] 12 io p5[3] 13 io p5[1] 14 io p1[7] i2c serial clock (scl) 15 io p1[5] i2c serial data (sda) 16 io p1[3] 17 io p1[1] crystal (xtalin), i2c serial clock (scl) 18 power vss ground connection. 19 io p1[0] crystal (xtalout), i2c serial data (sda) 20 io p1[2] 21 io p1[4] optional external clock input (extclk) 22 io p1[6] 23 io p5[0] 24 io p5[2] 25 io p3[0] 26 io p3[2] 27 io p3[4] 28 io p3[6] 29 input xres active high pin reset with internal pull down. 30 io p4[0] 31 io p4[2] 32 io p4[4] 33 io p4[6] 34 io i p2[0] direct switched capacitor block input. 35 io i p2[2] direct switched capacitor block input. 36 io p2[4] external analog ground (agnd) 37 io p2[6] external voltage reference (vref) 38 io i p0[0] analog column mux input. 39 io io p0[2] analog column mux input and column output. 40 io io p0[4] analog column mux input and column output. 41 io i p0[6] analog column mux input. 42 power vdd supply voltage. 43 io i p0[7] analog column mux input. 44 io io p0[5] analog column mux input and column output. 45 io io p0[3] analog column mux input and column output. 46 io i p0[1] analog column mux input. 47 io p2[7] 48 io p2[5] legend : a = analog, i = input, and o = output. * the mlf package has a center pad that must be connected to the ground (vss). mlf (top view) p2[5] p2[7] p0[1], ai p0[3], aio p0[5], aio p0[7], ai vdd p0[6], ai p0[4], aio p0[2], aio p0[0], ai p2[6], external vre f 10 11 12 a i, p2[3] a i, p2[1] p4[7] p4[5] p4[3] p4[1] smp p3[7] p3[5] p3[3] p3[1] p5[3] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[2], ai p2[0], ai p4[6] p4[4] p4[2] p4[0] xres p3[6] p3[4] p3[2] p3[0] p2[4], external agn d 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 p5[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss i2c sda, xtalout, p1[0] p1[2] extclk, p1[4] p1[6] p5[0] p5[2]
june 2004 document no. 38-12019 rev. *b 12 2. register reference this chapter lists the registers of the cy8c27x66 psoc device by way of mapping tables, in offset order. for detailed register infor- mation, reference the psoc? mixed signal array technical reference manual . 2.1 register conventions 2.1.1 abbreviations used the register conventions specific to this section are listed in the following table. 2.2 register mapping tables the psoc device has a total register address space of 512 bytes. the register space is also referred to as io space and is broken into two parts. the xoi bit in the flag register deter- mines which bank the user is currently in. when the xoi bit is set, the user is said to be in the ?extended? address space or the ?configuration? registers. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description rw read and write register or bit(s) r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
june 1, 2004 document no. 38-12019 rev. *b 13 cy8c27x66 preliminary data sheet 2. register reference register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw 41 asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw 42 asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw 43 asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw 44 asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw 45 asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw 46 asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 asc12cr0 88 rw rdi3ri c8 rw prt2ie 09 rw 49 asc12cr1 89 rw rdi3syn c9 rw prt2gs 0a rw 4a asc12cr2 8a rw rdi3is ca rw prt2dm2 0b rw 4b asc12cr3 8b rw rdi3lt0 cb rw prt3dr 0c rw 4c asd13cr0 8c rw rdi3lt1 cc rw prt3ie 0d rw 4d asd13cr1 8d rw rdi3ro0 cd rw prt3gs 0e rw 4e asd13cr2 8e rw rdi3ro1 ce rw prt3dm2 0f rw 4f asd13cr3 8f rw cf prt4dr 10 rw 50 asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw 51 asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw 52 asd20cr2 92 rw d2 prt4dm2 13 rw 53 asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw 54 asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw 55 asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw 56 asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw 57 asc21cr3 97 rw i2c_scr d7 # 18 58 asd22cr0 98 rw i2c_dr d8 rw 19 59 asd22cr1 99 rw i2c_mscr d9 # 1a 5a asd22cr2 9a rw int_clr0 da rw 1b 5b asd22cr3 9b rw int_clr1 db rw 1c 5c asc23cr0 9c rw int_clr2 dc rw 1d 5d asc23cr1 9d rw int_clr3 dd rw 1e 5e asc23cr2 9e rw int_msk3 de rw 1f rw 5f asc23cr3 9f rw int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp0_dr 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp1_dr 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp2_dr 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp3_dr 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbb10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbb10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbb10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbb10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11dr0 34 # acb01cr3 74 rw rdiolt1 b4 rw f4 dbb11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbb11cr0 37 # acb01cr2 77 rw b7 cpu_f f7 rl dcb12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcb12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcb12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcb12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcb13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw fc dcb13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw fd dcb13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcb13cr0 3f # acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
june 1, 2004 document no. 38-12019 rev. *b 14 cy8c27x66 preliminary data sheet 2. register reference register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 asc10cr0 80 rw rdi2ri c0 rw prt0dm1 01 rw 41 asc10cr1 81 rw rdi2syn c1 rw prt0ic0 02 rw 42 asc10cr2 82 rw rdi2is c2 rw prt0ic1 03 rw 43 asc10cr3 83 rw rdi2lt0 c3 rw prt1dm0 04 rw 44 asd11cr0 84 rw rdi2lt1 c4 rw prt1dm1 05 rw 45 asd11cr1 85 rw rdi2ro0 c5 rw prt1ic0 06 rw 46 asd11cr2 86 rw rdi2ro1 c6 rw prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw 48 asc12cr0 88 rw rdi3ri c8 rw prt2dm1 09 rw 49 asc12cr1 89 rw rdi3syn c9 rw prt2ic0 0a rw 4a asc12cr2 8a rw rdi3is ca rw prt2ic1 0b rw 4b asc12cr3 8b rw rdi3lt0 cb rw prt3dm0 0c rw 4c asd13cr0 8c rw rdi3lt1 cc rw prt3dm1 0d rw 4d asd13cr1 8d rw rdi3ro0 cd rw prt3ic0 0e rw 4e asd13cr2 8e rw rdi3ro1 ce rw prt3ic1 0f rw 4f asd13cr3 8f rw cf prt4dm0 10 rw 50 asd20cr0 90 rw gdi_o_in d0 rw prt4dm1 11 rw 51 asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw 54 asc21cr0 94 rw d4 prt5dm1 15 rw 55 asc21cr1 95 rw d5 prt5ic0 16 rw 56 asc21cr2 96 rw d6 prt5ic1 17 rw 57 asc21cr3 97 rw d7 18 58 asd22cr0 98 rw d8 19 59 asd22cr1 99 rw d9 1a 5a asd22cr2 9a rw da 1b 5b asd22cr3 9b rw db 1c 5c asc23cr0 9c rw dc 1d 5d asc23cr1 9d rw osc_go_en dd rw 1e 5e asc23cr2 9e rw osc_cr4 de rw 1f 5f asc23cr3 9f rw osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 w dcb02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp0_dr 6c rw ac ec dcb03in 2d rw tmp1_dr 6d rw ad ed dcb03ou 2e rw tmp2_dr 6e rw ae ee 2f tmp3_dr 6f rw af ef dbb10fn 30 rw acb00cr3 70 rw rdi0ri b0 rw f0 dbb10in 31 rw acb00cr0 71 rw rdi0syn b1 rw f1 dbb10ou 32 rw acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11fn 34 rw acb01cr3 74 rw rdiolt1 b4 rw f4 dbb11in 35 rw acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11ou 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl dcb12fn 38 rw acb02cr3 78 rw rdi1ri b8 rw f8 dcb12in 39 rw acb02cr0 79 rw rdi1syn b9 rw f9 dcb12ou 3a rw acb02cr1 7a rw rdi1is ba rw fls_pr1 fa rw 3b acb02cr2 7b rw rdi1lt0 bb rw fb dcb13fn 3c rw acb03cr3 7c rw rdi1lt1 bc rw fc dcb13in 3d rw acb03cr0 7d rw rdi1ro0 bd rw fd dcb13ou 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # 3f acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
june 2004 document no. 38-12019 rev. *b 15 3. electrical specifications this chapter presents the dc and ac electrical specifications of the cy8c27x66 psoc device. for the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. specifications are valid for -40 o c t a 85 o c and t j 100 o c, except where noted. figure 3-1a. voltage versus operating frequency figure 3-1b. voltage versus imo frequenc y the following table lists the units of measure that are used in this chapter. table 3-1: units of measure symbol unit of measure symbol unit of measure o c degree celsius w micro watts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nano ampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k ? kilohm ? ohm mhz megahertz pa pico ampere m ? megaohm pf pico farad a micro ampere pp peak-to-peak f micro farad ppm parts per million h micro henry ps picosecond s microsecond sps samples per second v micro volts sigma: one standard deviation vrms micro volts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=1 v a l i d o p e r a t i n g r e g i o n slimo mode=0
june 1, 2004 document no. 38-12019 rev. *b 16 cy8c27x66 preliminary data sheet 3. electrical specifications 3.1 absolute maximum ratings 3.2 operating temperature table 3-2: absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 ? +100 o c higher storage temperatures will reduce data retention time. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss-0.5 ? vdd+0.5 v ? dc voltage applied to tri-state vss-0.5 ? vdd+0.5 v i mio maximum current into any port pin -25 ? +50 ma i maio maximum current into any port pin configured as analog driver -50 ? +50 ma ? static discharge voltage 2000 ? ? v ? latch-up current ? ? 200 ma table 3-3: operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see ?thermal impedances? on page 37 . the user must limit the power con- sumption to comply with this requirement.
june 1, 2004 document no. 38-12019 rev. *b 17 cy8c27x66 preliminary data sheet 3. electrical specifications 3.3 dc electrical characteristics 3.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. 3.3.2 dc general purpose io specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 3-4: dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v i dd supply current ? 8 14 ma conditions are 5.0v, 25 o c, 3 mhz, 48 mhz dis- abled. vc1=1.5 mhz, vc2=93.75 khz, vc3=0.366 khz. i dd3 supply current ? 5 9 ma conditions are vdd=3.3v, t a =25 o c, cpu=3 mhz, 48 mhz=disabled, vc1=1.5 mhz, vc2=93.75 khz, vc3=0.366 khz. i ddp supply current when imo = 6 mhz ? 2 3 ma conditions are vdd=3.3v, t a =25 o c, cpu=3 mhz, 48 mhz=disabled, vc1=1.5 mhz, vc2=93.75 khz, vc3=0.366 khz. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. lower 3/4 temperature range. ? 3 10 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, -40 o c <=t a <= 55 o c. i sbh sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. higher 1/4 temperature range (hot). ? 4 25 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, 55 o c < t a <= 85 o c. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, internal slow oscillator, and 32 khz crystal oscillator active. lower 3/4 temperature range. ? 4 12 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, -40 o c <= t a <= 55 o c. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and 32 khz crystal oscillator active. higher 1/4 temperature range (hot). ? 5 27 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, 55 o c < t a <= 85 o c. v ref reference voltage (bandgap) 1.28 1.3 1.32 v trimmed for appropriate vdd. table 3-5: dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k ? r pd pull down resistor 4 5.6 8 k ? v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 io switch- ing, 4 per side) v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 io switch- ing, 4 per side) v il input low level ? ? 0.8 v vdd = 3.0 to 5.25 v ih input high level 2.1 ? v vdd = 3.0 to 5.25 v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c.
june 1, 2004 document no. 38-12019 rev. *b 18 cy8c27x66 preliminary data sheet 3. electrical specifications 3.3.3 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. the operational amplifier is a component of both the analog continuous time psoc blocks and the analog switched capacitor psoc blocks. the guaranteed specifications are measured in the analog continuous time psoc block. typical parameters apply to 5v at 25 c and are for design guidance only. important note do not use the combination of power = high and opamp bias = high for 3.3v operations. table 3-6: 5v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) low power input offset voltage (absolute value) mid power input offset voltage (absolute value) high power ?1.6 1.3 1.2 10 8 7.5 mv mv mv opamp bias = high. ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range. all cases, except high- est. power = high, opamp bias = high 0.0 ? vdd vdd-0.5 v v 0.5 ? cmrr oa common mode rejection ratio 60 ? ? db g oloa open loop gain 80 ? ? db v ohighoa high output voltage swing (worst case internal load) vdd-.01 ? ? v v olowoa low output voltage swing (worst case internal load) ? ? 0.1 v i soa supply current (including associated agnd buffer) power=low power=low, opamp bias=high power=medium power=medium, opamp bias=high power=high power=high, opamp bias=high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 60 ? ? db table 3-7: 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) low power input offset voltage (absolute value) mid power high power is 5 volt only ? ? 1.65 1.32 10 8 mv mv opamp bias = high. tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0 ? vdd v cmrr oa common mode rejection ratio 60 ? ? db g oloa open loop gain 80 ? ? db v ohighoa high output voltage swing (worst case internal load) vdd-.01 ? ? v v olowoa low output voltage swing (worst case internal load) ? ? 0.1 v i soa supply current (including associated agnd buffer) power=low power=low, opamp bias=high power=medium power=medium, opamp bias=high power=high ? ? ? ? ? 150 300 600 1200 2400 200 400 800 1600 3200 a a a a a psrr oa supply voltage rejection ratio 50 ? ? db
june 1, 2004 document no. 38-12019 rev. *b 19 cy8c27x66 preliminary data sheet 3. electrical specifications 3.3.4 dc analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 3-8: 5v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 ? vdd - 1.0 v r outob output resistance power = low power = high ? ? ? ? 1 1 ? ? v ohighob high output voltage swing (load = 32 ohms to vdd/2) power = low power = high 0.5 x vdd + 1.3 0.5 x vdd + 1.3 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.3 0.5 x vdd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 2 5 ma ma psrr ob supply voltage rejection ratio 40 ? ? db table 3-9: 3.3v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? ? ? 10 10 ? ? v ohighob high output voltage swing (load = 1k ohms to vdd/2) power = low power = high 0.5 x vdd + 1.0 0.5 x vdd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.0 0.5 x vdd - 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 1 8 ma ma psrr ob supply voltage rejection ratio 60 ? ? db
june 1, 2004 document no. 38-12019 rev. *b 20 cy8c27x66 preliminary data sheet 3. electrical specifications 3.3.5 dc switch mode pump specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. figure 3-2. basic switch mode pump circuit table 3-10: dc switch mode pump (smp) specifications symbol description min typ max units notes v pump 5v 5v output voltage at vdd from pump 4.75 5.0 5.25 v average, neglecting ripple. configuration with a 2 h induc- tor, 10 f capacitor, and schottky diode (see figure 3-2). smp trip voltage is set to 5.00v. v pump 3v 3v output voltage at vdd from pump 3.00 3.25 3.60 v average, neglecting ripple. configuration with a 2 h induc- tor, 10 f capacitor, and schottky diode (see figure 3-2). smp trip voltage is set to 3.25v. i pump available output current v bat = 1.5v, vo= 3.25v v bat = 1.8v, vo= 5.0v 8 5 ? ? ? ? ma ma configuration with a 2 h inductor, 10 f capacitor, and schottky diode (see figure 3-2). v bat 5v input voltage range from battery 1.8 ? 5.0 v configuration with a 2 h inductor, 10 f capacitor, and schottky diode (see figure 3-2). smp trip voltage is set to 5.00v. v bat 3v input voltage range from battery 1.0 ? 3.3 v configuration with a 2 h inductor, 10 f capacitor, and schottky diode (see figure 3-2). smp trip voltage is set to 3.25v. v batstart minimum input voltage from battery to start pump 1.1 ? ? v configuration with a 2 h inductor, 10 f capacitor, and schottky diode (see figure 3-2). ? v pump_line line regulation (over v bat range) ? 5 ? %v o configuration with a 2 h inductor, 10 f capacitor, and schottky diode (see figure 3-2). ? v pump_load load regulation ? 5 ? %v o configuration with a 2 h inductor, 10 f capacitor, and schottky diode (see figure 3-2). ? v pump_ripple output voltage ripple (depends on cap/ load) ? 25 ? mvpp configuration with a 2 h inductor, 10 f capacitor, load is 5ma, and schottky diode (see figure 3-2). ? efficiency 35 50 ? % configuration with a 2 h inductor, 10 f capacitor, load is 5ma, and schottky diode (see figure 3-2). smp trip voltage is set to 3.25v. f pump switching frequency ? 1.4 ? mhz configuration with a 2 h inductor, 10 f capacitor, and schottky diode (see figure 3-2). dc pump switching duty cycle ? 50 ? % configuration with a 2 h inductor, 10 f capacitor, and schottky diode (see figure 3-2). battery c1 d1 + psoc tm vdd vss smp v bat
june 1, 2004 document no. 38-12019 rev. *b 21 cy8c27x66 preliminary data sheet 3. electrical specifications 3.3.6 dc analog reference specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. the guaranteed specifications are measured through the analog continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power levels for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . table 3-11: 5v dc analog reference specifications symbol description min typ max units v bg5 bandgap voltage reference 5v 1.28 1.30 1.32 v ? agnd = vdd/2 a ct block power = high a. agnd tolerance includes the offsets of the local buffer in the psoc block. bandgap voltage is 1.3v 0.02v. vdd/2 - 0.017 vdd/2 vdd/2 + 0.017 v ? agnd = 2*bandgap a ct block power = high 2.52 2.60 2.72 v ? agnd = p2[4] (p2[4] = vdd/2) a ct block power = high p2[4] - 0.013 p2[4] p2[4] + 0.013 v ? agnd = bandgap a ct block power = high 1.27 1.3 1.33 v ? agnd = 1.6*bandgap a ct block power = high 2.03 2.08 2.13 v ? agnd column to column variation (agnd=vdd/2) a ct block power = high -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap ref control power = high vdd /2 + 1.218 vdd /2 + 1.3 vdd /2 + 1.382 v ? refhi = 3*bandgap ref control power = high 3.75 3.9 4.05 v ? refhi = 2*bandgap + p2[6] (p2[6] = 1.3v) ref control power = high p2[6] + 2.478 p2[6] + 2.6 p2[6] + 2.722 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) ref control power = high p2[4] + 1.218 p2[4] + 1.30 p2[4] + 1.382 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) ref control power = high p2[4] + p2[6] - 0.058 p2[4] + p2[6] p2[4] + p2[6] + 0.058 v ? refhi = 2*bandgap ref control power = high 2.50 2.60 2.70 v ? refhi = 3.2*bandgap ref control power = high 4.02 4.16 4.29 v ? reflo = vdd/2 ? bandgap ref control power = high vdd /2 - 1.369 vdd /2 - 1.30 vdd /2 - 1.231 v ? reflo = bandgap ref control power = high 1.20 1.30 1.40 v ? reflo = 2*bandgap - p2[6] (p2[6] = 1.3v) ref control power = high 2.489 - p2[6] 2.6 - p2[6] 2.711 - p2[6] v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) ref control power = high p2[4] - 1.368 p2[4] - 1.30 p2[4] - 1.232 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) ref control power = high p2[4] - p2[6] - 0.042 p2[4] - p2[6] p2[4] - p2[6] + 0.042 v
june 1, 2004 document no. 38-12019 rev. *b 22 cy8c27x66 preliminary data sheet 3. electrical specifications 3.3.7 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 3-12: 3.3v dc analog reference specifications symbol description min typ max units v bg33 bandgap voltage reference 3.3v 1.28 1.30 1.32 v ? agnd = vdd/2 a ct block power = high a. agnd tolerance includes the offsets of the local buffer in the psoc block. bandgap voltage is 1.3v 0.02v. vdd/2 - 0.017 vdd/2 - 0.0 vdd/2 + 0.017 v ? agnd = 2*bandgap a ct block power = high not allowed ? agnd = p2[4] (p2[4] = vdd/2) ct block power = high p2[4] - 0.009 p2[4] + 0.0 p2[4] + 0.009 v ? agnd = bandgap a ct block power = high 1.27 1.30 1.33 v ? agnd = 1.6*bandgap a ct block power = high 2.03 2.08 2.13 v ? agnd column to column variation (agnd=vdd/2) a ct block power = high -0.034 0.000 0.034 mv ? refhi = vdd/2 + bandgap ref control power = high not allowed ? refhi = 3*bandgap ref control power = high not allowed ? refhi = 2*bandgap + p2[6] (p2[6] = 0.5v) ref control power = high not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) ref control power = high not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) ref control power = high p2[4] + p2[6] - 0.042 p2[4] + p2[6] - 0.0 p2[4] + p2[6] + 0.042 v ? refhi = 2*bandgap ref control power = high 2.50 2.60 2.70 v ? refhi = 3.2*bandgap ref control power = high not allowed ? reflo = vdd/2 - bandgap ref control power = high not allowed ? reflo = bandgap ref control power = high not allowed ? reflo = 2*bandgap - p2[6] (p2[6] = 0.5v) ref control power = high not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) ref control power = high not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) ref control power = high p2[4] - p2[6] - 0.036 p2[4] - p2[6] + 0.0 p2[4] - p2[6] + 0.036 v table 3-13: dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.24 ? k ? c sc capacitor unit value (switch cap) ? 80 ? ff
june 1, 2004 document no. 38-12019 rev. *b 23 cy8c27x66 preliminary data sheet 3. electrical specifications 3.3.8 dc por, smp, and lvd specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 3-14: dc por, smp, and lvd specifications symbol description min typ max units notes v ppor0r v ppor1r v ppor2r vdd value for ppor trip (positive ramp) porlev[1:0]=00b porlev[1:0]=01b porlev[1:0]=10b ? 2.908 4.394 4.548 ? v v v v ppor0 v ppor1 v ppor2 vdd value for ppor trip (negative ramp) porlev[1:0]=00b porlev[1:0]=01b porlev[1:0]=10b ? 2.816 4.394 4.548 ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0]=00b porlev[1:0]=01b porlev[1:0]=10b ? ? ? 92 0 0 ? ? ? mv mv mv v lv d0 v lv d1 v lv d2 v lv d3 v lv d4 v lv d5 v lv d6 v lv d7 vdd value for lvd trip vm[2:0]=000b vm[2:0]=001b vm[2:0]=010b vm[2:0]=011b vm[2:0]=100b vm[2:0]=101b vm[2:0]=110b vm[2:0]=111b 2.863 2.963 3.070 3.920 4.393 4.550 4.632 4.718 2.921 3.023 3.133 4.00 4.483 4.643 4.727 4.814 2.979 a 3.083 3.196 4.080 4.573 4.736 b 4.822 4.910 a. always greater than 50 mv above ppor (porlev=00) for falling supply. b. always greater than 50 mv above ppor (porlev=10) for falling supply. v v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 vdd value for smp trip vm[2:0]=000b vm[2:0]=001b vm[2:0]=010b vm[2:0]=011b vm[2:0]=100b vm[2:0]=101b vm[2:0]=110b vm[2:0]=111b 2.963 3.033 3.185 4.110 4.550 4.632 4.719 4.900 3.023 3.095 3.250 4.194 4.643 4.727 4.815 5.000 3.083 3.157 3.315 4.278 4.736 4.822 4.911 5.100 v v v v v v v v v
june 1, 2004 document no. 38-12019 rev. *b 24 cy8c27x66 preliminary data sheet 3. electrical specifications 3.3.9 dc programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 3-15: dc programming specifications symbol description min typ max units notes i ccp supply current during programming or verify ? 10 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss+0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 3 6x50,000 and that no single block ever sees more than 50,000 cycles). the psoc devices use an adaptive algorithm to enhance endurance over the industrial temperature range (-40c to +85c ambient). any temperature range within a 50c span between 0c and 85c is considered constant with respect to endurance enhancements. for instance, if room temperature (25 c) is the nominal operating tempera- ture, then the range from 0c to 50c can be approximated by the constant value 25 and a temperature sensor is not needed. for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? ye ars
june 1, 2004 document no. 38-12019 rev. *b 25 cy8c27x66 preliminary data sheet 3. electrical specifications 3.4 ac electrical characteristics 3.4.1 ac chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. note see the individual user module data sheets for information on maximum frequencies for user modules. figure 3-3. pll lock timing diagram table 3-16: ac chip-level specifications symbol description min typ max units notes f imo internal main oscillator frequency 23.4 24 24.6 a mhz trimmed. utilizing factory trim values. f cpu1 cpu frequency (5v nominal) 0.93 24 24.6 a,b a. 4.75v < vdd < 5.25v. b. accuracy derived from internal main oscillator with appropriate trim for vdd range. mhz f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 b,c c. 3.0v < vdd < 3.6v. mhz f 48m digital psoc block frequency 0 48 49.2 a,b,d d. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on trimmi ng for 3.3v operation. mhz refer to the ac digital block specifica- tions below. f 24m digital psoc block frequency 0 24 24.6 b,e,d e. 3.0v < 5.25v. mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f pll pll frequency ? 23.986 ? mhz a multiple (x732) of crystal frequency. jitter24m2 24 mhz period jitter (pll) ? ? 600 ps t pllslew pll lock time 0.5 ? 10 ms t pllslewlow pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 250 500 ms t osacc external crystal oscillator startup to 100 ppm ? 300 600 f f. the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 uw maximum drive level 32.768 khz crystal. 3.0v vdd 5.5v, -40 o c t a 85 o c. ms jitter32k 32 khz period jitter ? 100 ns t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 a,c mhz trimmed. utilizing factory trim values. jitter24m1 24 mhz period jitter (imo) ? 600 ps f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s 24 mhz f pll pll e nable t pllslew pll gain 0
june 1, 2004 document no. 38-12019 rev. *b 26 cy8c27x66 preliminary data sheet 3. electrical specifications figure 3-4. pll lock for low gain setting timing diagram figure 3-5. external crystal oscillator startup timing diagram figure 3-6. 24 mhz period jitter (imo) timing diagram figure 3-7. 32 khz period jitter (eco) timing diagram 24 mhz f pll pll e nable t pllslewlow pll gain 1 32 khz f 32k2 32k s elect t os jitter24m1 f 24m jitter32k f 32k2
june 1, 2004 document no. 38-12019 rev. *b 27 cy8c27x66 preliminary data sheet 3. electrical specifications 3.4.2 ac general purpose io specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. figure 3-8. gpio timing diagram table 3-17: ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% tfallf tfalls trisef trises 90% 10% g pio pin
june 1, 2004 document no. 38-12019 rev. *b 28 cy8c27x66 preliminary data sheet 3. electrical specifications 3.4.3 ac operational amplifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. table 3-18: 5v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time to 0.1% for a 1v step (10 pf load, unity gain) power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high power = high, opamp bias = high ? ? ? ? ? ? ? ? ? 3.9 0.72 0.62 s s s s s s specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. t soa falling settling time to 0.1% for a 1v step (10 pf load, unity gain) power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high power = high, opamp bias = high ? ? ? ? ? ? ? ? ? 5.9 0.92 0.72 s s s s s s specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. sr roa rising slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? v/ s v/ s v/ s v/ s v/ s v/ s specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. sr foa falling slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? v/ s v/ s v/ s v/ s v/ s v/ s specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. bw oa gain bandwidth product power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? mhz mhz mhz mhz mhz mhz specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. e noa noise at 1 khz (power = medium, opamp bias = high) ? 70 ? nv/rt-hz
june 1, 2004 document no. 38-12019 rev. *b 29 cy8c27x66 preliminary data sheet 3. electrical specifications table 3-19: 3.3v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time to 0.1% of a 1v step (10 pf load, unity gain) power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high (3.3 volt high bias operation not supported) power = high, opamp bias = high (3.3 volt high power, high opamp bias not supported) ? ? ? ? ? ? ? ? ? ? 3.92 0.72 ? ? s s s s s s specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. t soa falling settling time to 0.1% of a 1v step (10 pf load, unity gain) power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high (3.3 volt high bias operation not supported) power = high, opamp bias = high (3.3 volt high power, high opamp bias not supported) ? ? ? ? ? ? ? ? ? ? 5.41 0.72 ? ? s s s s s s specification maximums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. sr roa rising slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high (3.3 volt high bias operation not supported) power = high, opamp bias = high (3.3 volt high power, high opamp bias not supported) 0.31 2.7 ? ? ? ? ? ? ? ? v/ s v/ s v/ s v/ s v/ s v/ s specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. sr foa falling slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high (3.3 volt high bias operation not supported) power = high, opamp bias = high (3.3 volt high power, high opamp bias not supported) 0.24 1.8 ? ? ? ? ? ? ? ? v/ s v/ s v/ s v/ s v/ s v/ s specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. bw oa gain bandwidth product power = low power = low, opamp bias = high power = medium power = medium, opamp bias = high power = high (3.3 volt high bias operation not supported) power = high, opamp bias = high (3.3 volt high power, high opamp bias not supported) 0.67 2.8 ? ? ? ? ? ? ? ? mhz mhz mhz mhz mhz mhz specification minimums for low power and high opamp bias, medium power, and medium power and high opamp bias levels are between low and high power levels. e noa noise at 1 khz (power = medium, opamp bias = high) ? 70 ? nv/rt-hz
june 1, 2004 document no. 38-12019 rev. *b 30 cy8c27x66 preliminary data sheet 3. electrical specifications 3.4.4 ac digital block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 3-20: ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency (> 4.75v) 49.2 4.75v < vdd < 5.25v. maximum block clocking frequency (< 4.75v) 24.6 3.0v < vdd < 4.75v. timer capture pulse width 50 a a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, with capture ? ? 24.6 mhz counter enable pulse width 50 a ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 a ? ? ns disable mode 50 a ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz spis maximum input clock frequency ? ? 4.1 ns width of ss_ negated between transmissions 50 a ? ? ns transmitter maximum input clock frequency ? ? 16.4 mhz receiver maximum input clock frequency ? 16 49.2 mhz 4.75v < vdd < 5.25v.
june 1, 2004 document no. 38-12019 rev. *b 31 cy8c27x66 preliminary data sheet 3. electrical specifications 3.4.5 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 3-21: 5v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 4 4 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 3.4 3.4 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.55 0.55 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 300 300 ? ? ? ? khz khz table 3-22: 3.3v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 4.7 4.7 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 4 4 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high .36 .36 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high .4 .4 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 200 200 ? ? ? ? khz khz
june 1, 2004 document no. 38-12019 rev. *b 32 cy8c27x66 preliminary data sheet 3. electrical specifications 3.4.6 ac external clock specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. 3.4.7 ac programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. table 3-23: 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0 ?24.24mhz ? high period 20.6 ? ?ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 3-24: 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 a a. maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum f requency and duty cycle requirements. 0 ?12.12mhz f oscext frequency with cpu clock divide by 2 or greater b b. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this cas e, the cpu clock divider will ensure that the fifty per- cent duty cycle requirement is met. 0 ?24.24mhz ? high period with cpu clock divide by 1 41.7 ? ?ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 3-25: ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 15 ? ms t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns
june 1, 2004 document no. 38-12019 rev. *b 33 cy8c27x66 preliminary data sheet 3. electrical specifications 3.4.8 ac i 2 c specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only or unless otherwise specified. figure 3-9. definition for timing for fast/standard mode on the i 2 c bus table 3-26: ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ? 100 a a. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input fil- ter. ? ? 0 50 ns s da scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c
may 2004 document no. 38-12019 rev. *b 34 4. packaging information 4.1 packaging dimensions this chapter illustrates the packaging specifications for the cy8c27x66 psoc device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. figure 4-1. 28-lead (300-mil) molded dip figure 4-2. 28-lead (210-mil) ssop 51-85014 - *c 51-85079 - *c
june 1, 2004 document no. 38-12019 rev. *b 35 cy8c27x66 preliminary data sheet 4. packaging information figure 4-3. 28-lead (300-mil) soic figure 4-4. 44-lead tqfp 51-85026 - *c 51-85064 - *b
june 1, 2004 document no. 38-12019 rev. *b 36 cy8c27x66 preliminary data sheet 4. packaging information figure 4-5. 48-lead (300-mil) ssop figure 4-6. 48-lead (7x7 mm) mlf 51-85061-c 51-85061 - *c 51-85152 - *a
june 1, 2004 document no. 38-12019 rev. *b 37 cy8c27x66 preliminary data sheet 4. packaging information 4.2 thermal impedances 4.3 capacitance on crystal pins table 4-1. thermal impedances per package package typical ja * 28 pdip 69 o c/w 28 ssop 96 o c/w 28soic tbd 44 tqfp 60 o c/w 48 ssop 69 o c/w 48 mlf 28 o c/w * t j = t a + power x ja table 4-2: typical package capacitance on crystal pins package package capacitance 28 pdip 3.5 pf 28 ssop 2.8 pf 28 soic tbd 44 tqfp 2.6 pf 48 ssop 3.3 pf 48 mlf 1.8 pf
june 1, 2004 document no. 38-12019 rev. *b 38 5. ordering information the following table lists the cy8c27x66 psoc device family?s key package features and ordering codes. 5.1 ordering code definitions table 5-1. cy8c27x66 psoc device family key features and ordering information package ordering code flash (kbytes) ram (bytes) switch mode pump temperature range digital psoc blocks (rows of 4) analog psoc blocks (columns of 3) digital io pins analog inputs analog outputs xres pin 28 pin (300 mil) dip CY8C27466-24PXI 32 1k yes -40 o c to +85 o c 8 12 24 12 4 yes 28 pin (210 mil) ssop cy8c27466-24pvxi 32 1k yes -40 o c to +85 o c 8 12 24 12 4 yes 28 pin (210 mil) ssop (tape and reel) cy8c27466-24pvxit 32 1k yes -40 o c to +85 o c 8 12 24 12 4 yes 28 pin (300 mil) soic cy8c27466-24sxi 32 1k yes -40 o c to +85 o c 8 12 24 12 4 yes 28 pin (300 mil) soic (tape and reel) cy8c27466-24sxit 32 1k yes -40 o c to +85 o c 8 12 24 12 4 yes 44 pin tqfp cy8c27566-24axi 32 1k yes -40 o c to +85 o c 8 12 40 12 4 yes 44 pin tqfp (tape and reel) cy8c27566-24axit 32 1k yes -40 o c to +85 o c 8 12 40 12 4 yes 48 pin (300 mil) ssop cy8c27666-24pvxi 32 1k yes -40 o c to +85 o c 8 12 44 12 4 yes 48 pin (300 mil) ssop (tape and reel) cy8c27666-24pvxit 32 1k yes -40 o c to +85 o c 8 12 44 12 4 yes 48 pin mlf cy8c27666-24lfxi 32 1k yes -40 o c to +85 o c 8 12 44 12 4 yes c y 8 c 27 xxx-spxx package type: thermal rating: px = pdip pb free c = commercial sx = soic pb free i = industrial pvx = ssop pb free e = extended lfx = mlf pb free ax = tqfp pb free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress microsystems company id: cy = cypress
june 2004 ? cypress microsystems, inc. 2004 ? document no. 38-12019 rev. *b 39 6. sales and service information to obtain information about cypress microsystems or psoc sales and technical support, reference the following information or go to the section titled ?getting started? on page 4 in this document. cypress microsystems 6.1 revision history 6.2 copyrights ? cypress microsystems, inc. 2004. all rights reserved. psoc? (programmable system-on-chip?) are trademarks of cypress microsys tems, inc. all other trademarks or registered trademarks referenced herein are property of the respective corporations. the information contained herein is subject to change without notice. cypress microsystems assumes no responsibility for the us e of any circuitry other than circuitry embodied in a cypress microsystems product. nor does it convey or imply any license under patent or other rights. cypress micro systems does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in s ignificant injury to the user. the inclusion of cypress microsystems products in life-support systems application implies that the manufacturer assumes all risk of such use an d in doing so indemnifies cypress micro- systems against all charges. cypress microsystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with cypress microsystems. 2700 162nd street sw building d lynnwood, wa 98037 phone: 800.669.0557 facsimile: 425.787.4641 web sites: company information ? http://www.cypress.com sales ? http://www.cypress.com/aboutus/sales_locations.cfm technical support ? http://www.cypress.com/support/login.cfm table 6-1. cy8c27x66 data sheet revision history document title: cy8c27466, cy8c27566, and cy8c27666 psoc mixed signal array preliminary data sheet document number: 38-12019 revision ecn # issue date origin of change description of change ** 133204 02/09/2004 sfv new silicon and document (revision **). *a 209441 03/15/2004 sfv changed block diagram on first page to match feature set description. *b 227242 06/01/2004 sfv changes to overview section, deleted 100-pin tqfp, added 28-pin soic, and signifi- cant changes to the electrical specifications section. title changed to reflect removal of cy8c27x866, along with removal or registers x,18h - x,1fh (in bank 0 and bank 1) from register reference chapter. distribution : external/public posting : none

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